|Resume of Mark S. Harris|
|(in PDF format) | (in RTF format) | (in MS Word format)|
MARK S. HARRIS
4105 Dauphine Dr. Austin, TX 78727
Hands-on senior Electrical/Hardware Engineer with extensive experience in System Architecture Design, Circuit Design, Logic Design, Microprocessor Interfacing. Strong ability to work individually or as part of a team from project conception through verification. Excellent ability to visualize solutions and solve technical issues.
Product Design Proficiency: System Architecture, Product Definition and Specification. Digital circuit design. Power distribution. PLD & FPGA design with Abel, Palasm and VHDL. Mentor Schematic Capture and Layout tools. Have designed cards for both high-run production and high performance testcard environments.
Application Software Proficiency: Microsoft Office including Word, Excel and MS Project. Adobe FrameMaker. FORTRAN, PASCAL, C, Python and various assembler languages. Experience with various operating systems including Windows, Mac and Unix.
MOTOROLA SEMICONDUCTOR DIVISION/FREESCALE SEMICONDUCTOR, Austin, TX 1982-2004
Senior Electrical Engineer, 1991-2004
Implemented flexible, distributed power distribution including power monitoring for several testcard systems allowing for unknown changes in future processors yet protecting the systems from user errors and electronic failures.
Designed flexible high-current plug-in power module boards to supply core power for processors under test, assuring improved response times and protecting from part obsolescence.
Created a series of Gigabit Ethernet Boards to test processor RMII, MII, GMII, TBI, RGMII, RTBI interfaces both with and without commercial PHY chips.
Designed highly configurable PCI backplane board for high-speed tests for modular "Bigfoot" testcard system providing initial debug and test platform for PCI controller chips.
Devised bridge module that worked on either the "Bigfoot" or the older "TC60X" testcard systems allowing the processor cards from the older system to be used on the newer system saving money and development time.
Designed complex four-processor 128-bit databus processor card capable of running in a master/checker mode for modular Bigfoot testcard system.
Produced processor card with high-speed L2 cache memory for Apple and Apple-clone computers. Sold over 4 million units to Apple.
Developed temperature control system for processor test using thermo-electric coolers coupled with vortex tubes. Vortex tubes turn compressed air into a cooling (or heating) air stream with no moving parts. This allowed precise control of a processor's temperature, cost less than $3000 and took up less space than the stand-alone freon type lab temperature control units, which cost over $15K.
Produced numerous processor cards for a variety of PowerPC processors, allowing these chips to be quickly tested, debugged and brought to market in less time and money than using production chip testers.
Created board with various differing line topologies, line characteristics and termination to test new processor IO drivers and to verify simulation models.
MOTOROLA COMPUTER GROUP, Austin, TX
Electrical Engineer, 1982-1991
Extended the VSBbus (secondary bus for VMEbus) from the original four inches to four feet allowing it to be used as a high-speed secondary bus for a family of remote IO and disk boards. Created a prototype proving the concepts and determining the appropriate cable characteristics needed. Designed the first IO board for this system.
Created In-house test and development VME board for the 68030 processor and the VME and VSB gate array chips. This card became the core of all future Motorola 68030 and 68040 VMEbus products.
Chief architect of the Motorola VME Master/Slave gate array chip. This became the VME interface used on all Motorola VMEbus processor boards for several years.
Pioneered first Motorola VMEbus memory board using SIP memory modules, the first using a mezzanine board and the first using ZIP memory packaging.
Designed the industry's first 32-bit VMEbus dynamic memory board, increasing sales of the companion 32-bit processor board.
Conducted the initial study of microcomputer-based workstations for electronic design for the Motorola Computer Group. Narrowed the choice down to two companies, Valid (now Cadence) and Mentor. Both are still in business while most of the others are long since gone.
Implemented an MMU based on the Motorola Versabus MMU card architecture using a Fujitsu gate array including the production test programs resulting in cost and board space savings.
VOUGHT CORPORATION, Grand Prairie, TX 1976-1981
Added graphics capability to major electrical network simulation program used on AIRTRANS transportation system.
UNIVERSITY OF TEXAS, Austin, TX 1976-1980
Carried out various graphics programming and software conversion projects for the Associate Dean of Engineering.
Selected and set up the first microcomputer system for the Chemical Engineering labs.
B.S. Electrical Engineering
University of Texas, Austin, TX
Mentor Comprehensive VHDL
High-Speed Digital Design by Dr. Howard Johnson
Advanced High-Speed Signal Propagation by Dr. Howard Johnson
"A Chip for All Boards". ESD, February 1988
"Die Dynamische Busanpassung Wird Unterstutzt". VMEbus, February 1988
"VMEchip Unterstutzt die Dynamische Busanpassung". Electronik, March 1988